LSR LSR Shift right one bit (memory or accumulator) LSR +-+-+-+-+-+-+-+-+ Operation: 0 -> |7|6|5|4|3|2|1|0| -> C N V - B D I Z C +-+-+-+-+-+-+-+-+ 0 . . . . . / / +----------------+-----------------------+---------+---------+----------+ | Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles| +----------------+-----------------------+---------+---------+----------+ | Accumulator | LSR A | $4A | 1 | 2 | | ZeroPage | LSR $FF | $46 | 2 | 5 | | ZeroPage,X | LSR $FF,X | $56 | 2 | 6 | | Absolute | LSR $FFFF | $4E | 3 | 6 | | Absolute,X | LSR $FFFF,X | $5E | 3 | 7 | +----------------+-----------------------+---------+---------+----------+ For penalty cycles on the 65816, check the desired addressing mode. 4510 Versions: +----------------+-----------------------+---------+---------+----------+ | Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles| +----------------+-----------------------+---------+---------+----------+ | ZeroPage | LSR $FF | $46 | 2 | 4r | | Accumulator | LSR A | $4A | 1 | 1s | | Absolute | LSR $FFFF | $4E | 3 | 5r | | ZeroPage,X | LSR $FF,X | $56 | 2 | 3pr | | Absolute,X | LSR $FFFF,X | $5E | 3 | 5pr | +----------------+-----------------------+---------+---------+----------+ p Add 1 if page boundary is crossed r Add 1 if clock speed is at 40 MHz s Instruction requires 2 cycles when CPU is run at 1 MHz or 2 MHZ